The present invention relates to a direct digital synthesizer (DDS) which provides fine deviation resolution for frequency modulation (FM) without requiring complex, costly or slow hardware.
A direct digital synthesizer is an electronic apparatus for generating cyclic waveforms by mapping discrete increment values to stored waveform data in a lookup table or memory. In a typical DDS circuit, a carrier frequency is generated by adding a constant phase increment number to an accumulation from the previous clock period. The phase accumulation is then mapped into a lookup table which addresses the corresponding cyclic waveform value, and the resulting digital waveform value is sent through a D/A converter and filtered to construct the final carrier frequency analog waveform. For frequency modulation, the phase increment input to the phase accumulator is no longer a constant but rather a function of the center frequency phase increment and a time varying phase increment corresponding to a modulation source usually multiplied by an FM deviation factor.
Frequency modulation can be implemented in various ways depending on design requirements. The simplest form of DDS frequency modulation is accomplished through the use of an adder which sums the selected carrier frequency related number with an instantaneous modulation value. The result is then used as a time variable phase increment input to the phase accumulator. This method is limited, however, due to its fixed FM frequency deviation.
To increase the controllability of FM frequency deviation, the instantaneous modulation value can be multiplied by a selected deviation factor and the product added to the selected carrier frequency related number. However, this method is usually slower and more expensive to implement due to the additional complexity of usual multiplication circuitry.
To reduce circuit complexity, an arithmetic shifter can be used instead of a multiplication unit. The arithmetic shifter serves to multiply the instantaneous modulation by a selectable deviation in powers of two. However, since bit shifters conventionally allow multiplication only in power of two increments, resolution of the FM modulation deviation is reduced, limiting the number of selectable channels that can be generated from the DDS.
The present invention relates to means for providing linear FM deviation control along with fine resolution controllability without having to use expensive, complex or slowly operating hardware.